module e203_nice_core(
  input         clock,
  input         reset,
  output        io_system_nice_active,
  output        io_system_nice_mem_holdup,
  output        io_cmdreq_ready,
  input         io_cmdreq_valid,
  input  [31:0] io_cmdreq_bits_nice_req_inst,
  input  [31:0] io_cmdreq_bits_nice_req_rs1,
  input  [31:0] io_cmdreq_bits_nice_req_rs2
);
  reg  REG; 
  assign io_system_nice_active = 1'h1; 
  assign io_system_nice_mem_holdup = 1'h1; 
  assign io_cmdreq_ready = REG; 
  always @(posedge clock or posedge reset) begin
    if (reset) begin
      REG <= 1'h0;
    end else begin
      REG <= io_cmdreq_valid;
    end
  end
endmodule
